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? semiconductor components industries, llc, 2011 march, 2011 ? rev. 17 1 publication order number: cat34c02/d cat34c02 2 kb i 2 c eeprom for ddr2 dimm serial presence detect description the cat34c02 is a 2 kb serial cmos eeprom, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each. it features a 16 ? byte page write buffer and supports both the standard (100 khz) as well as fast (400 khz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the entire memory) or by setting an internal write protect flag via software command (this protects the lower half of the memory). in addition to permanent software write protection, the cat34c02 also features jedec compatible reversible software write protection for ddr2 serial presence detect (spd) applications operating over the 1.7 v to 3.6 v supply voltage range. the cat34c02 is fully backwards compatible with earlier ddr1 spd applications operating over the 1.7 v to 5.5 v supply voltage range. features ? supports standard and fast i 2 c protocol ? 1.7 v to 5.5 v supply voltage range ? 16 ? byte page write buffer ? hardware write protection for entire memory ? software write protection for lower 128 bytes ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? this device is pb ? free, halogen free/bfr free and rohs compliant* figure 1. functional symbol sda scl wp cat34c02 v cc v ss a 2 , a 1 , a 0 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com pin configuration sda wp v cc v ss a 2 a 1 a 0 1 see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information scl tssop (y), tdfn (vp2), udfn (hu3), udfn (hu4) udfn ? 8 hu3 suffix case 517ax tssop ? 8 y suffix case 948al device address input a 0 , a 1 , a 2 serial data input/output sda serial clock input scl write protect input wp power supply v cc ground v ss function pin name pin function for the location of pin 1, please consult the corresponding package drawing. tdfn ? 8 vp2 suffix case 511ak udfn ? 8 ep hu4 suffix case 517az
cat34c02 http://onsemi.com 2 table 1. absolute maximum ratings parameter rating unit operating temperature ? 45 to +130 c storage temperature ? 65 to +150 c voltage on any pin with respect to ground (note 1) ? 0.5 to +6.5 v voltage on pin a 0 with respect to ground ? 0.5 to +10.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program/ erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode, v cc = 5 v, 25 c table 3. d.c. operating characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to +85 c, unless otherwise specified.) symbol parameter test conditions min max units i cc supply current v cc < 3.6 v, f scl = 100 khz 1 ma v cc > 3.6 v, f scl = 400 khz 2 i sb standby current all i/o pins at gnd or v cc t a = ? 40 c to +85 c v cc 3.3 v 1 a t a = ? 40 c to +85 c v cc > 3.3 v 3 i l i/o pin leakage pin at gnd or v cc 2 a v il input low voltage ? 0.5 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc + 0.5 v ol output low voltage v cc > 2.5 v, i ol = 3 ma 0.4 v cc < 2.5 v, i ol = 1 ma 0.2 table 4. pin impedance characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to +85 c, unless otherwise specified.) symbol parameter conditions max units c in (note 4) sda i/o pin capacitance v in = 0 v, f = 1.0 mhz, v cc = 5.0 v 8 pf other input pins 6 i wp (note 5) wp input current v in < v ih , v cc = 5.5 v 130 a v in < v ih , v cc = 3.6 v 120 v in < v ih , v cc = 1.7 v 80 v in > v ih 2 i a (note 5) address input current (a0, a1, a2) product rev h v in < v ih , v cc = 5.5 v 50 a v in < v ih , v cc = 3.6 v 35 v in < v ih , v cc = 1.7 v 25 v in > v ih 2 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 5. when not driven, the wp, a0, a1 and a2 pins are pulled down to gnd internally. for improved noise immunity, the internal pull -down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the inpu t high. to conserve power, as the input level exceeds the trip point of the cmos input buf fer (~ 0.5 x v cc ), the strong pull-down reverts to a weak current source.
cat34c02 http://onsemi.com 3 table 5. a.c. characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to +85 c) (note 6) symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 s t low low period of scl clock 4.7 1.3 s t high high period of scl clock 4 0.6 s t su:sta start condition setup time 4.7 0.6 s t hd:dat data hold time 0 0 s t su:dat data setup time 250 100 ns t r (note 7) sda and scl rise time 1000 300 ns t f (note 7) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 s t buf bus free time between stop and start 4.7 1.3 s t aa scl low to sda data out 3.5 0.9 s t dh data out hold time 100 100 ns t i (note 7) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 s t hd:wp wp hold time 2.5 2.5 s t wr write cycle time 5 5 ms t pu (notes 7 & 8) power ? up to ready mode 1 1 ms 6. test conditions according to ?a.c. test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. thermal characteristics (air velocity = 0 m/s, 4 layers pcb) (notes 9 and 10) part number package ja jc units cat34c02y tssop 64 37 c/w cat34c02vp2 tdfn 92 15 c/w cat34c02hu3 udfn 101 18 c/w cat34c02hu4 udfn 101 18 c/w 9. t j = t a + p d * ja , where: t j is the junction temperature, t a the ambient temperature, p d the power dissipation. example: cat34c02vp2, v cc = 3.0 v, i ccmax = 1 ma, t a = 85 c: t j = 85 c + 3 mw * 92 c/w = 85.276 c. 10. t j = t c + p d * jc , where: t c is the case temperature, etc. table 7. a.c. test conditions input levels 0.2 v cc to 0.8 v cc input rise and fall times 50 ns input reference levels 0.3 v cc , 0.7 v cc output reference levels 0.5 v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
cat34c02 http://onsemi.com 4 power ? on reset (por) the cat34c02 incorporates power ? on reset (por) circuitry which pr otects the internal logic against powering up in the wrong state. the cat34c02 will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por feature protects the device against ?brown ? out? failure following a temporary loss of power. pin description scl : the serial clock input pin accepts the serial clock generated by the master. sda : the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device address. these pins have on ? chip pull ? down resistors. wp : the write protect input pin inhibits all write operations, when pulled high. this pin has an on ? chip pull ? down resistor. functional description the cat34c02 supports the inter ? integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat34c02 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device address inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull ? up resistors. master and slave devices connect to the 2 ? wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 2). start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake ? up? call to all receivers. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop starts the internal write cycle (when following a write command) or sends the slave into standby mode (when following a read command). device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8 ? bit serial slave address. the first 4 bits of the slave address are set to 1010, for normal read/write operations (figure 3). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices. the last bit, r/w , specifies whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 4). the slave will also acknowledge the byte address and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. if the master acknowledges the data, then the slave continues transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by sending a stop to the slave. bus timing is illustrated in figure 5. start bit sda stop bit scl figure 2. start/stop timing
cat34c02 http://onsemi.com 5 101 0 device address figure 3. slave address bits a 0 a 1 a 2 r/w 189 start scl from master bus release delay (transmitter) bus release delay data output from transmitter data output from receiver figure 4. acknowledge timing (receiver) ack setup ( t su:dat ) ack delay ( t aa ) scl sda in sda out figure 5. bus timing t su:sto t buf t su:dat t su:sta t hd:sta t hd:dat t aa t f t dh t r t low t low t high write operations byte write in byte write mode the master sends a start, followed by slave address, byte address and data to be written (figure 6). the slave acknowledges all 3 bytes, and the master then follows up with a stop, which in turn starts the internal write operation (figure 7). during internal write, the slave will not acknowledge any read or write request from the master. page write the cat34c02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. a page is selected by the 4 most significant bits of the address byte following the slave address, while the 4 least significant bits point to the byte within the page. up to 16 bytes can be written in one write cycle (figure 8). the internal byte address counter is automatically incremented after each data byte is loaded. if the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a ?wrap ? around? fashion (within the selected page). the internal write cycle starts immediately following the stop. acknowledge polling acknowledge polling can be used to determine if the cat34c02 is busy writing or is ready to accept commands. polling is implemented by interrogating the device with a ?selective read? command (see read operations). the cat34c02 will not acknowledge the slave address, as long as internal write is in progress. delivery state the cat34c02 is shipped ?unprotected?, i.e. neither swp flag is set. the entire 2 kb memory is erased, i.e. all bytes are ffh.
cat34c02 http://onsemi.com 6 byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t figure 6. byte write timing stop condition start condition address ack 8th bit byte n scl sda figure 7. write cycle timing t wr bus activity: master sda line data n+p byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0 figure 8. page write timing 1891 8 byte address data scl sda wp figure 9. wp timing t hd:wp t su:wp a 0 a 7 d 7 d 0
cat34c02 http://onsemi.com 7 read operations immediate address read in standby mode, the cat34c02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. if that ?previous? byte was the last byte in memory, then the address counter will point to the 1 st memory byte, etc. when, following a start, the cat34c02 is presented with a slave address containing a ?1? in the r/w bit position (figure 10), it will acknowledge (ack) in the 9 th clock cycle, and will then transmit data being pointed at by the internal address counter. the master can stop further transmission by issuing a noack, followed by a stop condition. selective read the read operation can also be started at an address different from the one stored in the internal address counter. the address counter can be initialized by performing a ?dummy? write operation (figure 11). here the start is followed by the slave address (with the r/w bit set to ?0?) and the desired byte address. instead of following up with data, the master then issues a 2 nd start, followed by the ?immediate address read? sequence, as described earlier. sequential read if the master acknowledges the 1 st data byte transmitted by the cat34c02, then the device will continue transmitting as long as each data byte is acknowledged by the master (figure 12). if the end of memory is reached during sequential read, then the address counter will ?wrap ? around? to the beginning of memory, etc. sequential read works with either ?immediate address read? or ?selective read?, the only difference being the starting byte address. scl sda 8th bit stop no ack data out 8 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 10. immediate address read timing 9 slave address s n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address s t a r t figure 11. selective read timing a c k a c k bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address figure 12. sequential read timing
cat34c02 http://onsemi.com 8 software write protection the lower half of memory (first 128 bytes) can be protected against write requests by setting one of two software write protection (swp) flags. the permanent software write protection (pswp) flag can be set or read while all address pins are at regular cmos levels (gnd or v cc ), whereas the very high voltage v hv must be present on address pin a 0 to set, clear or read the reversible software write protection ( rswp ) flag. the d.c. operating conditions for rswp operations are shown in table 8. the swp commands are listed in t able 9. all commands are preceded by a start and terminated with a stop, following the ack or noack from the cat34c02. all swp related slave addresses use the pre ? amble: 0110 (6h), instead of the regular 1010 (ah) used for memory access. for pswp commands, the three address pins can be at any logic level, whereas for rswp commands the address pins must be at pre ? assigned logic levels. v hv is interpreted as logic ?1?. the v hv condition must be established on pin a 0 before the start and maintained just beyond the stop. otherwise an rswp request could be interpreted by the cat34c02 as a pswp request. the swp slave addresses follow the standard i 2 c convention, i.e. to read the state of the swp flag, the lsb of the slave address must be ?1?, and to set or clear a flag, it must be ? 0?. for w rite commands a dummy byte address and dummy data byte must be provided (figure 14). in contrast to a regular memory read, a swp read does not return data. instead the ca t34c02 will respond with noack if the flag is set and with ack if the flag is not set. therefore, the master can immediately follow up with a stop, as there is no meaningful data following the ack interval (figure 15). hardware write protection with the wp pin held high, the entire memory, as well as the swp flags are protected against w rite operations, see memory protection map below. if the wp pin is left floating or is grounded, it has no impact on the operation of the cat34c02. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the first data byte (figure 9). if the wp pin is high during the strobe interval, the cat34c02 will not acknowledge the data byte and the w rite request will be rejected. software write protectable (by setting the write protect flags) ffh 00h 7fh hardware write protectable (by connecting wp pin to v cc ) figure 13. memory protection map table 8. rswp d.c. operating conditions (note 11) symbol parameter test conditions min max units v hv a 0 overdrive (v hv ? v cc ) 1.7 v < v cc < 3.6 v 4.8 v i hvd a 0 high voltage detector current 0.1 ma v hv a 0 very high voltage 7 10 v i hv a 0 input current @ v hv 1 ma 11. to prevent damaging the cat34c02 while applying v hv , it is strongly recommended to limit the power delivered to pin a 0 , by inserting a series resistor (> 1.5 k ) between the supply and the input pin. the resistance is only limited by the combination of v hv and maximum i hvd . while the resistor can be omitted if v hv is clamped well below 10 v, it nevertheless provides simple protection against eos events. as an example: v cc = 1.7 v, v hv = 8 v, 1.5 k < r s < 15 k .
cat34c02 http://onsemi.com 9 table 9. swp commands wp pswp rswp x 1 xx no gnd 0x 0 yes x yes x yes yes 0x 0 yes x yes x no no x0x 1 yes x gnd gnd 1 x 001x no x gnd gnd 0 1 001x no gnd gnd gnd 0 0 0 0 1 0 yes x yes x yes yes gnd gnd 0 0 0 0 1 0 yes x yes x no no x gnd gnd 0 0 0 0 1 1 yes x gnd 1 x 011x no gnd gnd 0 x 0 1 1 0 yes x yes x yes yes gnd 0 x 0 1 1 0 yes x yes x no no x gnd 0 x 0 1 1 1 yes set rswp clear rswp 0110 slave address set pswp action control pin levels flag state ack ? write cycle ack ? ack ? address byte data byte b 7 to b 4 a 2 a 1 a 0 b 3 b 2 b 1 b 0 (note 12) (note 13) a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 a 2 a 1 a 0 v hv v hv v hv v hv v hv v hv v hv v hv v hv v cc v cc v cc v cc v cc v cc v cc 12. here a 2 , a 1 and a 0 are either at v cc or gnd. 13. 1 stands for ?set?, 0 stands for ?not set?, x stands for ?don?t care?. byte address slave address s a c k a c k data s t o p p bus activity: master sda line s t a r t x = don?t care x n o a c k or a c k figure 14. software write protect (write) xxxxxxx xxxxxxxx slave address s n o a c k or a c k s t o p p bus activity: master sda line s t a r t figure 15. software write protect (read)
cat34c02 http://onsemi.com 10 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
cat34c02 http://onsemi.com 11 package dimensions tdfn8, 2x3 case 511ak ? 01 issue a pin#1 identification e2 e a3 eb d a2 top view side view bottom view pin#1 index area front view a1 a l d2 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.30 1.40 1.50 e 3.00 e2 1.20 1.30 1.40 e 2.90 0.50 typ 3.10 l 0.20 0.30 0.40 a2 0.45 0.55 0.65
cat34c02 http://onsemi.com 12 package dimensions udfn8, 2x3 case 517ax ? 01 issue o e2 d2 k l e pin #1 index area pin #1 identification dap size 1.3 x 1.8 detail a d a1 b e a top view side view front view detail a bottom view a3 a a1 notes: (1) all dimensions are in millimeters. (2) complies with jedec mo-229. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.90 2.00 2.10 d2 1.50 1.60 1.70 e 3.00 e2 0.10 0.20 0.30 e 2.90 0.50 typ 3.10 l 0.30 0.35 0.40 k 0.10 ref
cat34c02 http://onsemi.com 13 package dimensions udfn8, 2x3 extended pad case 517az ? 01 issue o 0.065 ref copper exposed e2 d2 l e pin #1 index area pin #1 identification dap size 1.8 x 1.8 detail a d a1 b e a top view side view front view detail a bottom view a3 0.065 ref 0.0 - 0.05 a3 notes: (1) all dimensions are in millimeters. (2) refer jedec mo-236/mo-252. symbol min nom max a 0.45 0.50 0.55 a1 0.00 0.02 0.05 a3 0.127 ref b 0.20 0.25 0.30 d 1.95 2.00 2.05 d2 1.35 1.40 1.45 e 3.00 e2 1.25 1.30 1.35 e 2.95 0.50 ref 3.05 l 0.25 0.30 0.35 a
cat34c02 http://onsemi.com 14 example of ordering information cat34c02 (note 16) prefix device # suffix company id cat 34c02 y product number 34c02 i ? gt5 package i = industrial ( ? 40 c to +85 c) temperature range y: tssop vp2: tdfn (note 19) hu3: udfn (note 19) hu4: udfn t: tape & reel 4: 4000/reel (note 17) 5: 5000/reel (note 18) lead finish g: nipdau lead plating tape & reel (note 22) 14. all packages are rohs ? compliant (lead ? free, halogen ? free) 15. the standard lead finish is nipdau. 16. the device used in the above example is a cat34c02yi ? gt5 (tssop, industrial temperature, nipdau, 5000 pcs / reel) 17. the tdfn and udfn packages are available in 4000 pcs/reel (i.e., ca t34c02vp2i ? gt4, cat34c02hu3i ? gt4, ca t34c02hu4i ? gt4). 18. the tssop (y) package (i.e., cat34c02yi ? gt5) is available in 5000 pcs / reel. 19. not recommended for new designs. please replace with udfn 2 x 3 mm (hu4) package. 20. for gresham only die, please order the opns: cat 34c02yi-gt5a, cat34c02vp2igt4a, cat34c02hu3igt4a or cat34c02hu4igt4a. 21. for additional package and temperature options, please contact your nearest on semiconductor sales office. 22. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat34c02/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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